1. Field of the Invention
The present invention relates to a semiconductor wafer testing apparatus and a testing method of a semiconductor wafer.
2. Description of the Related Art
In a test of a semiconductor device by using a conventional semiconductor wafer testing apparatus, the whole of one semiconductor wafer is divided into n (n is a natural number larger than 1) regions, and m (m is a natural number smaller than n) regions are optionally selected from among the n regions. Then, a test of necessary test items is performed to semiconductor chips for the semiconductor devices formed on the m selected regions. All the test items are not necessary to semiconductor chips formed in the remaining (n−m) regions, and a test of selected test items is performed based on a cumulative defect percentage calculated from the test result to each of the semiconductor chips formed on the m regions. Thus, each test item having the cumulative defect percentage equal to or smaller than a specified threshold value is omitted to shorten the overall test time.
FIGS. 1A and 1B show a process flow of a test performed on a semiconductor wafer by a conventional semiconductor wafer testing apparatus. Upon start of the test of the semiconductor wafer, all test items (test item 1 to 5) are determined as necessary test items and a test of the test items is performed on m regions selected from n regions of a semiconductor wafer (step S1). Then, the determination of good product/defective product is carried out for each of the m regions based on the test result. Next, the number of defects and a cumulative defect percentage are determined for the semiconductor chips of a same type based on the test result carried out at the step S1 (step S2). At a time when the test of the necessary test items on the selected m regions is completed, a test of the necessary test items and a test of the selected test items are performed on the semiconductor chips formed on the (n−m) non-selected regions (step S3). In an examples shown in FIGS. 1A and 1B, the test item 1 and 2 are necessary test item, and the test items 3 to 5 are the selected test items. For the semiconductor chips formed on the (n−m) regions, the test of the necessary test items, i.e., a test of the test item 1 (step S4) and a test of the test item 2 (step S5) are first performed. A test of the selected test items is performed on the semiconductor chips, which passed the test of the necessary test items, and the semiconductor chips, which did not pass the test of the necessary test items, are handled as defective products.
When a test of the selected test item 3 starts, the cumulative defect percentage for the test item 3 is first checked (step S6). Here, if the cumulative defect percentage is 0.2% or more, the test of the test item 3 is actually performed (step S7). On the other hand, if the cumulative defect percentage is not larger than 0.2%, it is checked whether or not each of semiconductor chips formed on the m regions is defective (step S8). Here, if any of the semiconductor chips is defective, the test of the test item 3 is performed (step S7). If any of the semiconductor chips is not defective, the test of the test item 3 is omitted, and the semiconductor chips formed on the (n−m) regions pass the test of the test item 3 and are transferred as good products to the test of the next selected test item 4.
Operations in the test of the test items 4 and 5 are the same as that in the test of the test item 3, and thus the detailed description thereof is omitted here. When the test of the selected test items 3 to 5 is completed, products that have passed all the test items are handled as good products (step S15). On the other hand, if the products which have been determined to be defective in any one of the test items are handled as the detective products (step S16). When it is confirmed that the test of all the test items on all the semiconductor chips formed on the (n−m) regions has been completed (step S17), the cumulative defect percentages are obtained based on the test result of the test items 1 to (step S18), thus completing the test of the test items 1 to 5.
As described above, in order to incorporate the selected test items into the test by the conventional semiconductor wafer testing apparatus for omitting the test items, it is necessary that a chip manufacturing variation dependent on the region in the semiconductor wafer is small. For example, there is a case that process parameters such as a film thickness and dimension for physical evaluation and management concerning the chip structure and electrical parameters such as a threshold voltage of a transistor, an ON current value, an electrical resistance value of a resistor, and a capacitance of a capacitor are different depending on the location of the semiconductor chips. Alternately, there is a case that the process parameters and electrical parameters are different due to any manufacture-related trouble.
In such a case, if the test item is omitted based on the cumulative defect percentage for the test item, deterioration in the chip quality at shipment is caused.
In conjunction with the above description, Japanese laid Open Patent application (JP-P2004-266017A) discloses a “semiconductor wafer testing method”, in which the whole region of a semiconductor wafer is previously divided into n regions and a test is performed on each of the regions, m (n>m) regions of the n regions are optionally set and the test of necessary test items and selected test items is performed on the m regions. Good product/defective product determination is performed based on the test result and a test of the necessary test items is performed on the (n−m) regions and a test of the selected test items is performed in accordance with the cumulative defect percentages of the selected test items, and the final good product/defective product determination is performed based on the test result.
Also, Japanese Laid Open Patent application (JP-P2003-332189A) discloses a “semiconductor test system”. In this conventional example, a semiconductor wafer testing apparatus performs a test of a plurality of test items on semiconductor chips formed on a semiconductor wafer based on a test program. A management apparatus manages the test program used by this semiconductor wafer testing apparatus. The semiconductor wafer testing apparatus and the management apparatus are connected to each other through a communication line network. In the management apparatus, a collecting section collects test results of the plurality of test items on the semiconductor chips. A determining section determines the test items that can be omitted for all the semiconductor chips or the semiconductor chips satisfying a predetermined condition, based on the test result collected by the collecting section. A test program generating section generates a test program to omit the test items that have been determined by the determining section for all the semiconductor chips or semiconductor chips satisfying the predetermined condition. A transmitting section transmits the test program generated by the test program generating section to the semiconductor wafer testing apparatus. The semiconductor wafer testing apparatus performs the test in accordance with the test program transmitted from the transmitting section.
Moreover, Japanese Laid Open Patent application (JP-A-Heisei, 7-37959) discloses a “wafer test method”. In this conventional testing method of a wafer having a plurality of chips, a test of all test items is performed for a part of chips on a wafer whose arrangement position has been selected. A test of only the test items selected based on a test result is performed for the remaining chips on the wafer.
In accompaniment with the recent trend of a semiconductor device toward higher performance such as a multi-pin structure and a higher operation speed, a time required for a test of the semiconductor device has become longer. Thus, it is important to reduce the test time of the semiconductor wafer for semiconductor devices so as to improve a production efficiency and to reduce a cost of the semiconductor device. In order to reduce the test time, there is a case that some of test items are omitted. However, when the test items are simply omitted, deterioration in quality of the semiconductor wafer for the semiconductor devices is caused.